1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method of manufacturing the same obtained by improving structures of a cell transistor and a cell array and their formation methods in an electrically erasable programmable read-only memory (EEPROM) including a gate electrode having a three-layered structure.
2. Description of the Related Art
A large-capacity ultraviolet erasable programmable read-only memory (EPROM) has been developed as one of nonvolatile semiconductor memories to which data can be electrically written. In particular, as a technique to achieve high integration, a method of forming an EPROM cell by performing element isolation without using local oxidation is disclosed in U.S. Pat. No. 4,597,060.
A planar pattern of this EPROM cell is shown in FIG. 1A. FIG. 1B shows a sectional structure taken along the line of B--B in a row line (word line) direction, and FIG. 1C shows a sectional structure taken along the line of C--C in a column line (data line) direction. This EPROM is formed as follows. A first gate insulating film 171 is formed on the surface of a semiconductor substrate 170. A first polysilicon film 172 is deposited on the first gate insulating film, and is etched into stripes each having a predetermined width along a column direction of a cell array. Using the first polysilicon film 172 patterned into a striped shape in the column direction as a mask, an impurity diffusion region 173 of a conductivity type opposite to that of the substrate is formed in the semiconductor substrate to form source and drain regions of a cell transistor. A first insulating film 174 having a thickness substantially equal to that of the first polysilicon film 172 is buried between the patterned stripes of the first polysilicon film on the substrate. Thereafter, a second gate insulating film 175 is formed on the semiconductor substrate, and a second polysilicon film 176 is deposited on the second gate insulating film 175. The second polysilicon film 176, the second gate insulating film 175, and the first polysilicon film 172 are etched into stripes each having a predetermined width along a row direction of the cell array to form control and floating gate electrodes 176 and 172. Using the control gate electrode 176 pattered into a striped shape in the row direction as a mask, impurity ions of the same conductivity type as that of the substrate are implanted in an exposed surface of the semiconductor substrate. Therefore, an element isolation region 177 is formed to define an element region in the column direction.
In this case, since the first insulating film 174 having a large thickness is formed on the impurity diffusion regions 173 serving as the source and drain regions of the cell transistor, the ions are not implanted in the source and drain regions.
According to the above method of forming the EPROM cell, ions are implanted using the second polysilicon film (control gate electrode) 176 as a mask to form the element isolation region 177. Therefore, the element isolation region 177 does not have a fringe such as a bird beak formed by local oxidation. In addition, since the floating gate electrode 172 is formed in self-alignment when the control gate electrode 176 is formed, a margin for mask alignment is not required, thus preventing misalignment. Since the source and drain regions of the cells adjacent to each other in the row direction can be shared, excellently micropatterned cells can be formed.
In the above-mentioned EPROM cell having a two-layered gate electrode structure disclosed in U.S. Pat. No. 4,597,060, data cannot be electrically erased. An EPROM integrated circuit using this EPROM cell is undesirably expensive because a window through which ultraviolet rays are emitted must be formed in a package. After this EPROM integrated circuit is mounted on a printed circuit board, it is difficult to update data.
On the other hand, the conventional electrically erasable EEPROM cells can be clarified into the following two cells: a cell having a two-layered gate electrode structure consisting of control and floating gate electrodes; and a cell having a three-layered gate electrode structure, consisting of the above electrodes and an erase gate electrode, disclosed in U.S. Pat. No. 4,466,081. In the former EEPROM cell, during an erase operation, a high voltage is applied to a drain or a source of the cell transistor to utilize a tunnel current in a gate oxide film. Only a voltage which is equal to or lower than a breakdown voltage of a drain or source junction can be applied as the high voltage. In order to increase an erase efficiency, the thickness of the first gate oxide film between the floating gate electrode and the drain or the source must be decreased. With this decrease, the ratio of a capacitance between the floating gate electrode and the drain or the source, and a capacitance between the floating gate electrode and the semiconductor substrate is increased, and the ratio of capacitances between the control and floating gate electrodes, which affects writing characteristics, is decreased.
In contrast to this, in the latter EEPROM cell disclosed in U.S. Pat. No. 4,466,081, a high voltage is applied to the erase gate electrode during an erase operation, and the thickness of the first gate oxide film need not be decreased. Therefore, sufficient writing characteristics which are equal to those of the EPROM cell can be obtained without a decrease in ratio of capacitances between the control and floating gate electrodes, which affects writing characteristics.
In the conventional EEPROM disclosed in U.S. Pat. No. 4,466,081, a field oxide film is selectively formed by thermal oxidation using local oxidation (LOCOS) in order to isolate the cells adjacent to each other (element isolation). This local oxidation has an advantage in that an oxide film having a large thickness in a longitudinal direction with respect to the surface of the semiconductor substrate can be easily formed. However, at the same time, an oxide film is undesirably formed into a bird-beak shape along a lateral direction. Therefore, the element isolation region is undesirably spread, resulting in an increase in cell area. A contact area is also undesirably increased. In this structure, since the erase and control gate electrodes are perpendicular to each other, an unnecessary portion is undesirably formed when blocks are formed along the erase gate electrode.